Optimizing Floating Body Effect & AC performance in 65nm PD-SOI CMOS

Author

Huang, R.M. ; Chen, T.F. ; Hong, S.F. ; Lin, Y.H. ; Tsai, T.L. ; Liu, E.C. ; Yang, C.W. ; Hsieh, Y.S. ; Huang, Y.T. ; Pelloie, J.L. ; Tsai, C.T. ; Ma, G.H.

Author_Institution

United Microelectron. Corp. (UMC), Tainan

fYear

2007

fDate

1-4 Oct. 2007

Firstpage

107

Lastpage

108

Abstract

An advanced partially-depleted (PD) silicon-on-insulator (SOI) CMOS device was optimized with full consideration of the floating body effect (FBE) using channel and S/D engineering. By adjusting channel and S/D implants´ species and dosage, the S/D doping profiles across transistor sidewall junction will be shown to reduce floating body effects and sidewall junction capacitance. Reduced sidewall junction capacitance results in higher performance in AC operation. In this paper we successfully demonstrated the optimized devices that exhibit suppression floating body effect, and lower ring oscillator (RO) static leakage and active power consumption at the same propagation delay.

Keywords

CMOS integrated circuits; nanoelectronics; silicon-on-insulator; AC performance; PD-SOI CMOS; S/D doping profiles; active power consumption; advanced partially-depleted silicon-on-insulator CMOS device; floating body effect; lower ring oscillator; sidewall junction capacitance; size 65 nm; static leakage; transistor sidewall junction; CMOS technology; Capacitance; Doping profiles; Energy consumption; Impact ionization; Implants; Leakage current; MOS devices; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2007 IEEE International

Conference_Location

Indian Wells, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-0879-5

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2007.4357875

Filename

4357875