DocumentCode
1872775
Title
P-slice based efficient speculative multithreading
Author
Ranjan, Rakesh ; Marcuello, Pedro ; Latorre, Fernando ; González, Antonio
Author_Institution
Comput. Archit. Dept., Univ. Politec. de Catalunya, Barcelona, Spain
fYear
2009
fDate
16-19 Dec. 2009
Firstpage
119
Lastpage
128
Abstract
Microprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single threaded applications to benefit from the additional cores to improve their execution time. Speculative multithreading (SpMT) has been proposed in the past to boost performance of irregular applications in multi-core environments. In this work, we study the main bottlenecks of these architectures, such as the memory behavior and the pre-computation slices and propose two novel schemes that allow SpMT to get 25% average speedup over single threaded execution. We propose Selective Replication as a technique to improve the performance of the SpMT memory system. This technique does not introduce additional traffic in the bus and improves the performance of a conventional SpMT memory model by 6% on average and up to 21% for some applications. Also, we propose a scheme called Slice Specialization that reduces the number of instructions in the pre-computation slices by adapting the slice to every single speculative thread spawned. The later proposal outperforms previous schemes with slices by 15% and overall, both techniques combined achieve an improvement of 20% over a conventional SpMT processor.
Keywords
microprocessor chips; multi-threading; multiprocessing systems; P-slice; SpMT memory system; microprocessor industry; multicore environments; selective replication technique; single threaded execution; slice specialization scheme; speculative multithreading; transistors; Algorithms; Computer architecture; Concurrent computing; Costs; Hardware; Multithreading; Parallel processing; Proposals; Runtime; Yarn; Multithreading; Speculation; TLS;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing (HiPC), 2009 International Conference on
Conference_Location
Kochi
Print_ISBN
978-1-4244-4922-4
Electronic_ISBN
978-1-4244-4921-7
Type
conf
DOI
10.1109/HIPC.2009.5433216
Filename
5433216
Link To Document