Physical IP for SOI design infrastructure

ASIC design is today achieved by mixing different physical IP blocks including standard cells, memory compilers, IO and analog blocks when needed. The circuits are designed using a given EDA flow, starting from high-level functional description (RTL netlist) and going down to the physical implementation. This process involves logical synthesis to achieve the required functionality, timing analysis, power analysis and area optimization performed before and after routing of the different blocks. This process has become quite complex and necessitates many iterations to reach the expected result in term of speed, power consumption and area. As SOI processes become more popular and are now considered for use in ASIC beyond the traditional use for CPU, it has become crucial to put in place the corresponding physical IP libraries.