Delay Fault Detection Problems in Circuits Feautring a Low Combination Depth

The growing bandwidth of digital ICs is often achieved using high speed pipelines that feature a low combinational depth. In this context, the combinational fraction of path delays becomes comparable to the timing parameters ensuring the correct logic behavior of memory elements (flip-flops and pulsed latches). In the presence of delay defects, the probability that faulty signal transitions give rise to a non-logic behavior of memory elements is no longer negligible with respect to the probability to sample a valid (correct or wrong) logic value as it is traditionally considered by the delay fault model. This phenomenon is here analyzed at the electrical level showing that it cannot be fully accounted by the path delay fault model. Hence, we propose a new fault model that accounts for memory elements possibly behaving in a non-logic way. This model has been validated at the electrical level in the presence of distributed defects and resistive opens.