• DocumentCode
    1873834
  • Title

    Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs

  • Author

    Kamal, Mustaffa ; Koohi, Somayyeh ; Hessabi, Shaahin

  • Author_Institution
    Sharif Univ. of Technol., Tehran
  • fYear
    2007
  • fDate
    26-28 Sept. 2007
  • Firstpage
    179
  • Lastpage
    187
  • Abstract
    Power dissipation, energy consumption of CUT and also number of required test vectors for obtaining predetermined fault coverage are the most important criteria used for evaluating the quality of a test pattern generator (TPG). In this paper, we analyze LFSR´s flexibility in improving these evaluation criteria for TPG. Usually, we are interested in considering these different criteria simultaneously, while looking for the best configuration. For this purpose, we use genetic algorithm as our optimization algorithm and define some new optimization functions and analyze the capability of LFSR to reduce power, energy and test delay under these functions. From our experimental results on ISCAS´89 and ITC´99, we show that power dissipation of CUT is approximately independent of different optimization functions, and so energy consumption only depends on the number of test vectors. On the other hand, test delay depends on the optimization function, which enforces us to include delay term in the function to avoid test vector increment. Finally, by analyzing energy efficiency values and behavior of energy consumption in terms of fault coverage, under different optimization functions, we show that delay is a suitable optimization function for LFSRs with respect to the number of test vectors, power dissipation, energy consumption and energy efficiency.
  • Keywords
    automatic test pattern generation; energy conservation; energy consumption; fault diagnosis; genetic algorithms; logic testing; shift registers; LFSR-based TPG; empirical analysis; energy consumption; energy efficiency; fault coverage; genetic algorithm; linear feedback shift register; optimization algorithm; power dissipation; test delay; test pattern generator; Automatic testing; Built-in self-test; Delay; Energy consumption; Optimization methods; Pattern analysis; Power dissipation; Power engineering and energy; Power generation; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
  • Conference_Location
    Rome
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-2885-4
  • Type

    conf

  • Filename
    4358385