Evolvable hardware with Boolean functions network implementation

In this paper we present an evolvable hardware structure based on a Boolean functions network implemented with the basic multiplexer circuit and configured by a hardware genetic algorithm. Even if evolvable hardware is a large research area (beginning in 1996) the main problem which remains is integration in one single chip of the entire system which consists in reconfigurable circuit and the evolvable algorithm: the build of intrinsic evolvable hardware. Another problem is how to increase the convergence speed as to can be used in real time applications. In our paper we present a possible solution to these problems. One single chip (Xilinx Spartan 3) integration is performed by using a multiplexer network as reconfigurable circuit and a hardware genetic algorithm based on internal block RAM memories, shift registers and basic circuits. To increase the convergence speed parallel sorting/testing blocks are used and the entire system has a pipeline architecture which allow the execution in same time of the genetics operators, testing and fitness computation.