Proposed best practices in silicon photonics layout vs. schematic physical verification

Emerging silicon photonics technology offers the intriguing promise of significant performance improvements coupled with manageable production costs. The fast propagation speed of optical signals minus the encumbrance of physical parasitic degradation implies very fast processing speeds at very low power, while implementing photonics in well-established silicon processes also promises relatively inexpensive manufacturing expenses. However, as silicon photonics design migrates from research into commercial production, photonics designers must embrace some fundamental process changes before fully realizing these benefits. This paper proposes best practices for ensuring accurate extraction and layout vs. schematic (LVS) comparison of silicon photonics circuits.