Using thermal cycle and temperature / voltage testing to reduce the incidence of resistive / open reliability defects

Continued scaling of CMOS technologies has challenged the capability of “traditional” reliability defect screens. The increases in power due to scaling has diminished the effectiveness and increased the cost of performing accelerated voltage based screens such as Burn-in. In addition, the smaller geometries in the Back End Of Line (BEOL) has meant more susceptibility to opens/resistive mechanisms which have not been screened well by “traditional” voltage based screens. Through experimentation, it was determined that the use of thermal cycle and temperature/voltage corner testing significantly diminished the magnitude of opens/resistive mechanisms and also afforded some screening of “traditional” “shorting” mechanisms.