Analysis of the reliability impact on high-k metal gate SRAM with assist-circuit

Assist circuits for SRAM have become a foreseeable solution for Vmin improvement. In this work, we characterized SRAM Vmin behaviors with read-write assist circuit before and after high temperature operating life (HTOL) stress. Our study demonstrated that read assist with suppressed wordline design not only improved time zero SRAM Vmin window, but also benefited to relieve BTI induced Read Vmin degradation after HTOL as read assist alleviates read disturb and stabilizes read operation. However, the wordline voltage needs to adjust carefully to reduce write performance impact when turning on read assist. Write assist used in this study shows over 200mV improvement at time zero with negative bitline boost, we have also evaluated write assist negative bias window and verified no reliability concern with proper bias setting.