A reliable method for the extraction of the lateral position of defects in ultra-scaled MOSFETs

We propose a new method to determine the lateral position of border traps in MOSFETs. The approach is based on the dependence of the trap-induced threshold voltage shift on the drain bias which is sensitive to the trap position. This follows from the results obtained with both technology computer aided design (TCAD) simulations and with a compact model. Using our novel method we extract the lateral position of a number of experimentally observed traps. We show that even in the presence of random dopants the lateral position of the trap can be determined with a precision of several nanometers. Considering random dopants is one of the key features of our method. The compact model essentially allows to avoid time consuming TCAD simulations without significant loss of accuracy.