Improved two-stage DC-coupled gate driver for enhancement-mode SiC JFET

Normally-OFF SiC VJFETs have been proved to be advantageous as a ¿drop-in¿ replacement of MOSFETs and IGBTs in a variety of applications. As this device´s acceptance continues to grow, developers are investigating optimized driver methods that will yield the best possible switching performance leading to higher system efficiencies. This paper presents new results for an alternative and more optimized gate driver to the capacitive coupled driver used in past literature. Additionally switching energy measurements are documented for the 50 mOhm enhancement-mode SiC VJFET in the newly optimized two-stage, DC-coupled gate driver and compared against past results obtained using the initial driver design. Specific design guidelines are included for achieving the best possible results using the two stage gate driver design presented here.