DocumentCode
1881499
Title
A test pattern for three-dimensional latch-up analysis
Author
De Munari, Ilaria ; Menozzi, Roberto ; Davoli, Massimo ; Fantini, Fausto
Author_Institution
Dipartimento di Ingegneria dell´´Inf., Parma Univ., Italy
fYear
1993
fDate
22-25 Mar 1993
Firstpage
103
Lastpage
109
Abstract
By means of both cross-section and layout two-dimensional (2D) numerical simulations, three-dimensional (3D) latch-up interactions are demonstrated to significantly influence the latch-up behavior of a typical CMOS structure. A 3D latch-up test pattern is designed to allow the experimental study of such effects. The first measurement results show complex behaviors that can be overlooked if common 2D test patterns are used
Keywords
CMOS integrated circuits; circuit layout; integrated circuit testing; 2D numerical simulations; CMOS structure; complex behaviors; cross-section simulation; layout simulation; test patterns; three-dimensional latch-up analysis; CMOS digital integrated circuits; CMOS process; CMOS technology; Circuit simulation; Circuit testing; MOSFET circuits; Numerical simulation; Pattern analysis; Physics; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location
Sitges
Print_ISBN
0-7803-0857-3
Type
conf
DOI
10.1109/ICMTS.1993.292886
Filename
292886
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