A test structure for E-beam testing

Author

Madrenas, Jordi ; Cabestany, Joan

Author_Institution

Dept. d´´Enginyeria Electron., Univ. Politecnico de Catalunya, Barcelona, Spain

fYear

1993

fDate

22-25 Mar 1993

Firstpage

89

Lastpage

94

Abstract

A structure to improve the e-beam logic testability of complex VLSI and wafer-scale integration (WSI) circuits is proposed. This structure makes possible the generation of internal logic states without any extra external connection pads by means of a low-energy and observation-compatible electron beam. Since these internal logic states reflect the presence/absence of the electron beam on a point of the IC, the beam can interact with the IC functionality. The structure is intended for CMOS technology, and is based on parasitic bipolar transistors compatible with standard CMOS processes

Keywords

CMOS integrated circuits; VLSI; electron beam testing; integrated logic circuits; logic testing; CMOS technology; E-beam testing; IC functionality; complex VLSI; connection pads; internal logic states; logic testability; observation-compatible electron beam; parasitic bipolar transistors; test structure; wafer-scale integration; Bipolar transistors; CMOS logic circuits; CMOS process; CMOS technology; Circuit testing; Electron beams; Logic circuits; Logic testing; Very large scale integration; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on

Conference_Location

Sitges

Print_ISBN

0-7803-0857-3

Type

conf

DOI

10.1109/ICMTS.1993.292888

Filename

292888