DocumentCode
1881619
Title
Generalized delay optimization of resistive interconnections through an extension of logical effort
Author
Venkat, Kartik
Author_Institution
Silicon Graphics, Inc.
fYear
1993
fDate
3-6 May 1993
Firstpage
2106
Lastpage
2109
Keywords
CMOS logic circuits; Delay; Geometry; Integrated circuit interconnections; Inverters; Logic functions; Logic gates; Optimization; Repeaters; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693097
Link To Document