• DocumentCode
    1881986
  • Title

    Transactional Memory Architecture and Implementation for IBM System Z

  • Author

    Jacobi, C. ; Slegel, T. ; Greiner, D.

  • Author_Institution
    IBM Syst. & Technol. Group, Poughkeepsie, NY, USA
  • fYear
    2012
  • fDate
    1-5 Dec. 2012
  • Firstpage
    25
  • Lastpage
    36
  • Abstract
    We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.
  • Keywords
    cache storage; instruction sets; memory architecture; cache design; enterprise class software RAS; instruction set architecture features; microprocessor generation; multiprocessor shared memory infrastructure; next generation IBM system z CPU; transactional memory architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Vancouver, BC
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-4673-4819-5
  • Type

    conf

  • DOI
    10.1109/MICRO.2012.12
  • Filename
    6493605
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1881986