DocumentCode
1882020
Title
Generic test chip formats for ASIC-oriented semiconductor process development
Author
Weber, Charles
Author_Institution
Hewlett-Packard Corp., Palo Alto, CA, USA
fYear
1993
fDate
22-25 Mar 1993
Firstpage
247
Lastpage
252
Abstract
A novel approach towards test chip and test structure design is accelerating the introduction of application specific integrated circuit (ASIC)-oriented CMOS process generations. Specialized test chips address quality manufacturability and process integration issues within the proper time frame. Six generic test chip design formats repeat from generation to generation with scaled layout rules
Keywords
CMOS integrated circuits; application specific integrated circuits; integrated circuit manufacture; integrated circuit testing; quality control; semiconductor process modelling; ASIC-oriented semiconductor process development; CMOS process; generic test chip; process integration; quality manufacturability; scaled layout rules; test chip formats; test structure design; Application specific integrated circuits; Chip scale packaging; Circuit testing; Computer aided manufacturing; Fabrication; Life estimation; Process control; Random access memory; Semiconductor device testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on
Conference_Location
Sitges
Print_ISBN
0-7803-0857-3
Type
conf
DOI
10.1109/ICMTS.1993.292911
Filename
292911
Link To Document