Session 21 overview: Successive-approximation ADCs

For many years, successive-approximation ADCs have been the standard architecture for very-low-power and low-speed applications. For moderate-to-high speed applications, other ADC structures such as flash and pipeline have been traditionally the architecture of choice. However, in the recent past, the increasing speed of devices in scaled CMOS technologies has enabled successive-approximation ADCs to penetrate the medium-to-high-speed application domains. Additionally, the lower intrinsic gain of transistors and opamps in scaled CMOS has made the successive-approximation structures more appealing, because in most such implementations an opamp is often not required. Therefore, much recent research activity has been invested in this type of ADCs. In this session, newest advancements in SAR ADCs that push resolution, FoM, and/or speed to the next level are presented.