DocumentCode
1883844
Title
An 18b 12.5MHz ADC with 93dB SNR
Author
Hurrell, Christopher Peter ; Lyden, Colin ; Laing, D. ; Hummerston, Derek ; Vickery, M.
Author_Institution
Analog Devices, Newbury, UK
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
378
Lastpage
379
Abstract
This paper describes an 18b 12.5 MHz ADC that uses a pipeline of 2 successive-approximation ADCs. Both ADCs, one before and one after a closed loop residue amplifier, determine 2 bits plus one redundant bit per bit trial. The converter core consumes 105 mW and achieves a dynamic range of 93 dB. The chip is implemented in a 0.25 ¿m/0.5 ¿m CMOS process and occupies 6 mm2.
Keywords
amplifiers; analogue-digital conversion; SNR; analogue-digital conversion; closed loop residue amplifier; converter core; frequency 12.5 MHz; power 105 mW; signal to noise ratio; size 0.25 mum; size 0.5 mum; successive-approximation ADC; word length 18 bit; Adders; Calibration; Capacitance; Capacitors; Dynamic range; Feedback; Sampling methods; Switches; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433829
Filename
5433829
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