DocumentCode
1886084
Title
A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality
Author
Jae-Sung Yoon ; Jeong-hyun Kim ; Hyo-Eun Kim ; Won-Young Lee ; Seok-Hoon Kim ; Kyusik Chung ; Jun-Seok Park ; Lee-Sup Kim
Author_Institution
KAIST, Daejeon, South Korea
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
336
Lastpage
337
Abstract
A parallel unified processor for graphics and vision is developed. It achieves 371.9G0PS/W in full operation through a 6-way VLIW datapath, reconfigurable processing elements for graphics and vision mode, and a pixel arranger for data-level parallelism. The pose-estimation engine achieves 0.89 μW/fps for marker-based augmented reality.
Keywords
augmented reality; instruction sets; parallel machines; pose estimation; VLIW datapath; augmented reality; data level parallelism; graphics unified processor; pixel arranger; pose estimation engine; reconfigurable processing elements; vision unified processor; Augmented reality; CMOS technology; Engines; Graphics; Hardware; Parallel processing; Reduced instruction set computing; State estimation; Tiles; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433907
Filename
5433907
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