A scalable massively parallel processor for real-time image processing

Author

Kurafuji, T. ; Haraguchi, Masanobu ; Nakajima, Masahiro ; Gyoten, T. ; Nishijima, T. ; Yamasaki, Hirofumi ; Imai, Yuki ; Ishizaki, M. ; Kumaki, Takeshi ; Okuno, Yoshihiro ; Koide, Tetsushi ; Mattausch, Hans Jurgen ; Arimoto, Keisuke

Author_Institution

Renesas Technol., Itami, Japan

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

334

Lastpage

335

Abstract

A processor with 2048 4 b grained processor elements (PE) and a 2 Mb SRAM is implemented in 65 nm CMOS and occupies a 5.29 mm² die. It achieves 200 MHz operation at 1.0 V and outputs peak power efficiency of 310 GOPS/W. The peak performance reached 191 GOPS at 560 MHz and 1.2 V in the double frequency mode. The processor can be optimized for both power and area by changing the number of PEs from 256 to 2048.

Keywords

CMOS integrated circuits; digital signal processing chips; parallel processing; real-time systems; CMOS; SRAM; frequency 200 MHz; grained processor elements; peak power efficiency; real-time image processing; scalable massively parallel processor; voltage 1.0 V; Adders; CMOS process; Circuits; Data processing; Energy consumption; Frequency; Image processing; Pipelines; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433910

Filename

5433910