• DocumentCode
    1886597
  • Title

    A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

  • Author

    Yen-Chuan Huang ; Tai-Cheng Lee

  • Author_Institution
    Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    300
  • Lastpage
    301
  • Abstract
    A 10 b pipelined ADC employs opamp and time-sharing techniques to reduce the power consumption and silicon area. The presented ADC needs only one opamp to complete the 10 b conversion. The chip is fabricated in a 90 nm digital CMOS process and occupies 0.058 mm2. It operates at 100 MS/S and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0 V supply.
  • Keywords
    AC-DC power convertors; CMOS integrated circuits; elemental semiconductors; nanoelectronics; operational amplifiers; silicon; Si; digital CMOS process; opamp; pipelined ADC; power 4.5 mW; power consumption; silicon area; size 90 nm; time sharing technique; voltage 1 V; CMOS technology; Calibration; Circuits; Clocks; Degradation; Energy consumption; Frequency; Power generation; Threshold voltage; Time sharing computer systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433927
  • Filename
    5433927
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1886597