DocumentCode
1887638
Title
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration
Author
Yoshioka, Michifumi ; Ishikawa, Kenji ; Takayama, Teruou ; Tsukamoto, Sanroku
Author_Institution
Fujitsu Labs., Kawasaki, Japan
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
384
Lastpage
385
Abstract
A 10 b 50 MS/s SAR ADC is presented that uses comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The prototype in 65 nm CMOS achieves 56.9 dB SNDR at 50 MS/s and consumes 820 μW from a 1.0 V supply including the digital calibration circuits.
Keywords
analogue-digital conversion; calibration; comparators (circuits); digital-analogue conversion; CDAC; PVT variation compensation; SAR ADC; SNDR; comparator offset calibration; internal clock frequency control; linearity error calibration; on-chip digital calibration; storage capacity 10 bit; successive approximation ADC; Calibration; Capacitance; Capacitors; Clocks; Delay; Error correction; Frequency conversion; Linearity; Tuning; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433965
Filename
5433965
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