DocumentCode
1888451
Title
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS
Author
Jae-sun Seo ; Ron Ho ; Lexau, J. ; Dayringer, M. ; Sylvester, Dennis ; Blaauw, D.
Author_Institution
Univ. of Michigan, Ann Arbor, MI, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
182
Lastpage
183
Abstract
We present circuits for efficient repeaterless on-chip wires. A transmitter sends RZ pulses to a clockless hysteresis receiver using a 3-tap FIR filter to control ISI. Partly overlapped bits double bandwidth using adaptive pre-emphasis. A 90 nm CMOS testchip shows bandwidth density of 4.4 Gb/s/¿m over 5 mm on-chip links with 0.34 pJ/b energy consumption.
Keywords
CMOS integrated circuits; FIR filters; intersymbol interference; transceivers; CMOS; FIR filter; ISI control; adaptive pre-emphasis; clockless hysteresis receiver; energy consumption; intersymbol interference; low-energy on-chip signaling; on-chip links; on-chip wires; transmitter; Bandwidth; Circuit testing; Clocks; Energy consumption; Finite impulse response filter; Hysteresis; Intersymbol interference; Repeaters; Transmitters; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433993
Filename
5433993
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