• DocumentCode
    1888561
  • Title

    A 20Gb/s 40mW equalizer in 90nm CMOS technology

  • Author

    Ibrahim, S.A. ; Razavi, Behzad

  • Author_Institution
    Univ. of California, Los Angeles, CA, USA
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    170
  • Lastpage
    171
  • Abstract
    A linear equalizer with 9dB of boost and a 1-tap speculative half-rate DFE compensate for 24dB of channel loss at 10GHz, generating an output with a BER less than 1012 and an eye opening of 0.32UI. The circuit consumes 40mW from a 1V supply at 20Gb/s.
  • Keywords
    CMOS integrated circuits; equalisers; error statistics; BER; CMOS technology; bit errror rate; channel loss; complementary metal-oxide-semiconductor; frequency 10 GHz; gain 9 dB; linear equalizer; power 40 mW; voltage 1 V; Bit error rate; CMOS technology; Circuits; Clocks; Decision feedback equalizers; Energy consumption; Inductors; Latches; Resistors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433999
  • Filename
    5433999
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1888561