DocumentCode
1888800
Title
An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluation
Author
Mo, Fan ; Zhang, Yihua ; Yu, Jun ; Zhang, Qianling
Author_Institution
ASIC, Fudan Univ., Shanghai, China
fYear
2000
fDate
9-9 June 2000
Firstpage
13
Lastpage
14
Abstract
In this paper, we present a novel cubic-polynomial evaluation algorithm. It is suitable for VLSI implementation and the computational cost is reduced to about 66% of the previously reported method.
Keywords
VLSI; application specific integrated circuits; iterative methods; polynomials; systolic arrays; VLSI implementation; computational cost; cubic-polynomial evaluation; iterative methods; systolic arrays; Analog-digital conversion; Application specific integrated circuits; Computational efficiency; Instruments; Iterative algorithms; Iterative methods; Performance evaluation; Polynomials; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location
Yokohama, Japan
Print_ISBN
0-7803-5973-9
Type
conf
DOI
10.1109/ASPDAC.2000.835055
Filename
835055
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