Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Author

Khakifirooz, A. ; Kangguo Cheng ; Jagannathan, B. ; Kulkarni, Parag ; Sleight, J.W. ; Shahrjerdi, Davood ; Chang, J.B. ; Sungjae Lee ; Junjun Li ; Huiming Bu ; Gauthier, R. ; Doris, B. ; Shahidi, Ghavam

Author_Institution

IBM, Albany, NY, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

152

Lastpage

153

Abstract

We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, and demonstrate that all devices including analog, I/O, and passive devices can be fabricated in the thin silicon layer. Excellent device matching, g_m/g_ds scaling to small gate length, good RF performance, and absence of history effect are the main features of the ETSOI technology.

Keywords

CMOS integrated circuits; low-power electronics; silicon-on-insulator; Si; circuit design; complementary metal-oxide-semiconductor; device matching; fully depleted extremely thin SOI; low power CMOS; low power technology; passive devices; silicon on insulator; size 20 nm; size 22 nm; thin silicon layer; CMOS technology; Diodes; Fluctuations; History; Logic devices; Parasitic capacitance; Random access memory; Resistors; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5434014

Filename

5434014