Radiation effects in fully-depleted CMOS/SOS

Device modeling was used to investigate features of thin-film devices and to explore the consequences of radiation exposure. A simple model for radiation-induced charge accumulation at the silicon-sapphire interface was adopted. The model calculates only the distribution of interface charge, not the actual charge density as a function of radiation dose. Two bias conditions, gate high and drain high, were considered. As an example of the results, normalized trapped charge distributions in the silicon-sapphire interface for the gate-high bias condition are presented; in this case, charge accumulation tends to be along the channel length dimension under the body near the mesa edge. For the drain-high case, charge accumulation is preferentially in the width dimension near the source end of the device. From these distributions the dependence of subthreshold characteristics on peak interface charge has been calculated to illustrate the strong sensitivity of the fully-depleted device to charge accumulation