A new CMAC neural network architecture and its ASIC realization

A new VLSI architecture of the CMAC neural network, called CCMAC, which is composed of an embedded content addressable memory (CAM) is proposed. The CCMAC can determine whether the addressing content resides in the memory or not faster. If a match doesn´t occur, the activated address is stored in a vacant cell of the CAM. With this mechanism, memory utilization rate can be improved to 100% and control noise can be suppressed. Moreover, the associated mask function, which is triggered while the CAM is full, can improve control performance. Comparison between CCMAC and a conventional CMAC is examined on the truck backer-upper control simulation. A CMAC ASIC chip has been implemented using a 0.6-/spl mu/m CMOS technology under 3.3- or 2.5-V supply voltages after obtaining design trade-off. The chip contains 0.33-million transistors and operates at 20 MH for a 2.5-V supply with only 10-mW power dissipation.