DocumentCode
1891454
Title
A graph build algorithm for layout compaction using binary search tree
Author
Arun, A. ; Saxena, Sanjaya K. ; Chowdhury, Debashis Roy
Author_Institution
LSI Design Semicond. Complex Ltd., Punjab, India
fYear
1988
fDate
7-9 Jun 1988
Firstpage
715
Abstract
The authors describe an efficient graph build algorithm for one-dimensional compaction of virtual grid symbolic layouts following the constraint graph approach. The algorithm uses a binary search tree to geometrically sort the symbolic groups. This produces significant reduction in the number of comparisons between the groups. The binary search tree approach strives to overcome the limitations of the existing methods and generates a correct graph with fewer constraints. The graph build algorithm has been implemented in Pascal on PRIME 750 computer as part of a compaction program in a virtual grid layout system
Keywords
VLSI; circuit layout CAD; PRIME 750 computer; Pascal; VLSI layout; binary search tree; comparisons reduction; constraint graph approach; fewer constraints; graph build algorithm; layout CAD; layout compaction; one-dimensional compaction; virtual grid layout system; virtual grid symbolic layouts; Algorithm design and analysis; Binary search trees; Buildings; Compaction; Design automation; Large scale integration; Shadow mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo
Type
conf
DOI
10.1109/ISCAS.1988.15025
Filename
15025
Link To Document