Performance improvement of differential static CMOS logic family

This article proposes an improved structure of conventional Differential Static Circuit Logic (DSCL) using two new loads and Drain-bulk connected model of bulk-driven MOS transistors. The circuit topology of the proposed DSCL and its performance factors are clarified. The performance of the improved DSCL is compared to the conventional DSCL circuits in terms of delay, power, power-delay-product, output capacitances and output transient current. Delay optimization of the proposed DSCL studied and it shows the full preserve of static properties in DSCL too. The performance evaluation of both circuits was carried out using HSPICE simulations, 180nm technology and power supply of 1.8v. In the same optimum operational condition, the proposed improved DSCL achieved power-delay-product (PDP), 22% less than conventional DSCL Using load No.1 and 15% reduction of PDP by applying load No. 2.