DocumentCode
1892034
Title
Dynamic range estimation for systems with control-flow structures
Author
Wu, Bin
Author_Institution
Adv. Micro Devices, Inc., Sunnyvale, CA, USA
fYear
2012
fDate
19-21 March 2012
Firstpage
370
Lastpage
377
Abstract
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore the overall circuit area, delay and power consumption. Many analytical approaches are proposed for dynamic range estimation. However, because of the intractable nature of control-flow structures, all currently available methods consider only the systems consisting of pure dataflow structures/operations, while the general digital applications always contain some control-flow structures, such as conditional branches and loops, that depend on the randomness of inputs or other variables. Failing to handle general control-flow structures seriously restricts the applicability of analytical methods for dynamic range estimation, and makes lack-of-insight and costly profiling the only solutions for many applications. In this paper, we propose the first analytical method capable of handling general control-flow structures (especially random branches and loops) by utilizing a powerful mathematic tool, polynomial chaos expansion (PCE). Our method brings the application scope of analytical method for range estimation to general systems with control-flow structures for the first time, and it achieves high accuracy and orders of magnitude more efficiency than profiling.
Keywords
application specific integrated circuits; chaos; hardware description languages; high level synthesis; integrated circuit design; polynomials; program control structures; ASIC; analytical method; control flow structure; datapath bitwidth reduction; polynomial chaos expansion; random branch; random loop; Accuracy; Chaos; Control systems; Data models; Dynamic range; Estimation; Polynomials; Dynamic range; algorithm conversion; bitwidth; branch; control-flow structures; fixed-point; floating-point; high-level synthesis; loop; polynomial chaos expansion (PCE);
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1948-3287
Print_ISBN
978-1-4673-1034-5
Type
conf
DOI
10.1109/ISQED.2012.6187520
Filename
6187520
Link To Document