DocumentCode
1893026
Title
Technology aware design and design aware technology
Author
Maex, K. ; Stucchi, M. ; Bamal, M. ; Grossar, E. ; Dehaene, W. ; Papanikolaou, A. ; Miranda, M. ; Catthoor, F.
Author_Institution
IMEC, Leuven, Belgium
fYear
2005
fDate
9-11 May 2005
Firstpage
77
Lastpage
81
Abstract
Scaling beyond the 90nm node is not automatically accompanied by a lower energy per function and a better performance. This is true both for transistors and interconnects. Since IC performance remains important in a competitive world, the success of scaled technologies are to be coupled with innovative circuit and system design strategies. Therefore, a much higher synergy between technology and design communities becomes mandatory. The tile concept needs also to be refined in view of the role it plays in the system as the highest level of abstraction for technology optimization in terms of the tile size and the tile performance it should also serve as a granularity measure in system design.
Keywords
integrated circuit design; integrated circuit interconnections; design aware technology; integrated circuit design; integrated circuit interconnects; technology aware design; technology optimization; transistors; Boundary conditions; Circuits and systems; Costs; Delta-sigma modulation; Integrated circuit yield; Leakage current; Physics; Power generation economics; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN
0-7803-9081-4
Type
conf
DOI
10.1109/ICICDT.2005.1502596
Filename
1502596
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