Low temperature metal-based cell integration technology for gigabit and embedded DRAMs

Author

Yoshida, M. ; Kumauchi, T. ; Kawakita, K. ; Ohashi, N. ; Enomoto, H. ; Umezawa, T. ; Yamamoto, N. ; Asano, I. ; Tadaki, Y.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

41

Lastpage

44

Abstract

An advanced memory cell structure with poly/metal word lines and metal bit lines is proposed. The thermal processes are carefully designed for the metal-based cell to be consistent with narrow gap filling, wet cleaning, planarity, and the contact process. The extremely low temperature process also helps suppress the short channel effect of the MOS transistors. The fully self-aligned contact and via-hole technology provides the minimum memory cell area. This technology is promising for future gigabit DRAMs and embedded DRAMs.

Keywords

CMOS memory circuits; DRAM chips; integrated circuit metallisation; integrated circuit technology; MOS transistors; contact process; embedded DRAM; gigabit DRAM; integration technology; low temperature metal-based cell process; memory cell structure; metal bit lines; narrow gap filling; planarity; poly/metal word lines; self-aligned contact technology; self-aligned via-hole technology; short channel effect suppression; thermal processes; wet cleaning; Annealing; Capacitors; Filling; Integrated circuit interconnections; Planarization; Process design; Random access memory; Rapid thermal processing; Temperature; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649451

Filename

649451