A wafer bonded SOI structure for intelligent power ICs

Author

Ohoka, Tsukasa ; Yoshitake, Tomonobu ; Kikuchi, Hiroaki ; Okonogi, Kensuke

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1993

fDate

18-20 May 1993

Firstpage

119

Lastpage

123

Abstract

A novel isolation structure has been developed for intelligent power ICs based on wafer bonding technology. In this method of isolation, an Si-SiO₂ coexistent surface is directly bonded to a silicon base wafer, resulting in SiO₂ films buried in part of the composite substrate. This structure makes it easy to isolate control circuits from power output devices. It enables the monolithic integration of output devices having high-current and high-breakdown voltage capability and CMOS control circuits. The authors describe the details of this technology and its application to an intelligent power IC which needs a breakdown voltage of more than 600 V

Keywords

MOS integrated circuits; power integrated circuits; power transistors; semiconductor-insulator boundaries; wafer bonding; 600 V; CMOS control circuits; HV MOSFET; Si-SiO₂ coexistent surface; breakdown voltage; composite substrate; direct bonding technology; elemental semiconductor; intelligent power ICs; monolithic integration; wafer bonding technology; Fabrication; Intelligent structures; Isolation technology; Power integrated circuits; Semiconductor films; Silicon; Substrates; Surface finishing; Voltage control; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1993. ISPSD '93., Proceedings of the 5th International Symposium on

Conference_Location

Monterey, CA

ISSN

1063-6854

Print_ISBN

0-7803-1313-5

Type

conf

DOI

10.1109/ISPSD.1993.297120

Filename

297120