A compact pipelined architecture with high-throughput for context-based binary arithmetic coding

This paper presents a novel pipelined ASIC architecture for the context-based binary arithmetic encoder in JPEG2000. With the employment of a compact 4-stage pipelined architecture, the proposed encoding architecture is able to process every input symbol within one clock cycle. This architecture not only overcomes the problem of unfixed pipeline stages emerging from the uncertain times of renormalizations during the encoding phase, but also reduces the number of registers necessitated by the pipeline structure.