An incremental floorplanning algorithm for temperature reduction

Integrating a large number of transistors in a limited silicon area causes chip temperature to increase rapidly. High temperature incurs a number of design problems such as high leakage power consumption and unreliable operations. It is worthwhile to note that the peak temperature of a chip may go down by finding an optimal floorplanning. Especially, it is very important to consider temporal correlation of temperature states because the temperature of a block may go up or down depending on the temperatures of the surrounding blocks. In this paper, we propose a set of floorplanning techniques to reduce the peak temperature.