High-temperature reliability behavior of SSI-flash E/sup 2/PROM devices

Author

De Blauwe, J. ; Wellekens, D. ; Groeseneken, G. ; Haspeslagh, L. ; Van Houdt, J. ; Deferm, L. ; Maes, H.E.

Author_Institution

IMEC, Leuven, Belgium

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

93

Lastpage

96

Abstract

The high-temperature (T) reliability of merged-transistor Source Side Injection (SSI) Flash NVM devices is evaluated in terms of endurance and SILC-related disturbs, and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room T, Program/Erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to enhanced charge emission, but also in a reduction of the read-disturb margin. Also, a bake of 72 hrs. at 250/spl deg/C does not cure the generated damage and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.

Keywords

EPROM; electron traps; integrated circuit reliability; integrated memory circuits; internal stresses; leakage currents; 150 degC; 250 degC; 72 h; SILC-related disturbs; SSI-flash E/sup 2/PROM devices; endurance; enhanced charge emission; high-temperature reliability behavior; merged-transistor source side injection devices; oxide traps; program/erase cycling; read-disturb margin; stress-induced leakage current; Degradation; Filling; PROM; Phonons; Solid modeling; Stress; Tellurium; Temperature dependence; Temperature measurement; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.649472

Filename

649472