Pseudo-symmetric functional decision diagrams

A new algorithm for generating a regular logic structure, pseudo-symmetric functional decision diagrams (PSFDDs), for completely specified Boolean functions is presented. The diagrams are based on functional decision diagrams (FDDs) and pseudo-symmetric binary decision diagrams (PSBDDs). A Davio expansion is used to generate the initial vertex subfunctions which are then modified by a new join-XOR operation. The operation allows one to combine adjacent vertices such that the function is represented as a regular pseudo-symmetric network which can be easily implemented with an array of AND/XOR gates. Due to the regular structure the interconnection length is known from representation so the post-layout delays can be accurately predicted before the layout is completed