Criticality-based routing for FPGAS with reverse body bias switch box architectures

The use of reverse body bias (RBB) in circuit design is recognized to be a viable strategy for managing leakage power, a burning issue as process nodes continue to shrink beyond the 20nm realm. This technique is especially useful to FPGAs, which are able to tune RBB modes on-the-fly, offering leakage power reduction with very little impact to circuit speed. Most works today on RBB as applied to FPGAs are limited to the optimizations at the CLB level. We present a different architectural enhancement - the RBB switch box, and a routing algorithm deploying net criticality ranking that exploits the flexibility of such an architecture. Compared to the non-RBB baseline, our scheme yields an average of 64.74% and 38.92% savings in the routing leakage power and the total power respectively (contributed solely by our routing architecture), with slight improvements to timing. The area overhead associated with our enhancement is also very small, with one unit area of biasing circuit 140×100μm² supporting ~340 switch boxes i.e. a 13×13 CLB array.