DocumentCode
1897651
Title
Managing the FPGA memory wall: Custom computing or vector processing?
Author
Naylor, Matthew ; Fox, Paul J. ; Markettos, A. Theodore ; Moore, Simon W.
Author_Institution
Comput. Lab., Univ. of Cambridge, Cambridge, UK
fYear
2013
fDate
2-4 Sept. 2013
Firstpage
1
Lastpage
6
Abstract
Managing the memory wall is critical for massively parallel FPGA applications where data-sets are large and external memory must be used. We demonstrate that a soft vector processor can efficiently stream data from external memory whilst running computation in parallel. A non-trivial neural computation case study illustrates that multi-core vector processing coupled with careful layout of data structures performs similarly to an elaborate full-custom memory controller and execution pipeline. The vector processing version was far simpler to code so we encourage others to consider vector machines before contemplating a full-custom architecture on FPGA.
Keywords
data structures; field programmable gate arrays; microprocessor chips; FPGA memory wall; custom computing; data structures; data-sets; execution pipeline; external memory; full-custom architecture; full-custom memory controller; massively parallel FPGA applications; multicore vector processing; nontrivial neural computation; soft vector processor; vector machines; vector processing version; Bandwidth; Field programmable gate arrays; Neurons; Pipelines; Random access memory; Registers; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on
Conference_Location
Porto
Type
conf
DOI
10.1109/FPL.2013.6645538
Filename
6645538
Link To Document