The CMOS GATE FOREST: High Performance Semicustom ASIC´s for Complex Logic and Memory

As an extension of the existing sea of gates concept, the GATE FOREST concept will be presented, together with its implementation in CMOS technology. The GATE FOREST distinguishes itself from the older sea of gates concept in its different architecture, which is based on a hierarchical view of both complex logic and design approach. The micro architecture of the GATE FOREST is characterized by the use of both gate isolation and geometrical isolation, a high degree of connectivity and an optimal transparancy for route-through signals. The macro architecture is characterized by a channelless approach. The GATE FOREST (micro)architecture is specialized towards the implementation of dynamic logic. However static logic structures can also be efficiently implemented. The use of both static and dynamic logic is supported with two cell libraries. The dynamic cell library has three sub-libraries based on three different categories of dynamic logic: domino logic, cascode voltage switch logic (CVSL) and sample-set differential logic (SSDL). The GATE FOREST implementation is based on a scalable, lambda based design rule set, enabling easy conversion down to one micron CMOS technology. To demonstrate the effectiveness of the GATE FOREST approach, a number of basic logic functions and memory cells are evaluated, using the area per transistor ratio as characterization. A particular design example--a five input XOR- is used to compare a number of different implementation possibilities.