Magnitude modulation on reconfigurable computing devices

The control of the envelope´s peak power by reducing overall peak-to-average power (PAPR) of transmitted RF signals can improve significantly the power efficiency of wireless communication systems both for single-carrier (SC) and multi-carrier (MC) transmissions. Multi-stage polyphase magnitude modulation (MPMM) has been recently proposed as an efficient PAPR reduction technique for SC signals. In this paper, we present a proof-of-concept prototype implementation in FPGA of the MPMM method. A prior study of the MPMM performance under fixed-point arithmetic is carried on, justifying decision criteria taken on MPMM´s design targeted to FPGA.