Design and FPGA implementation of a 100 Gbit/s optical transport network processor

This paper presents the design and architecture of an OTN Processor, fully implemented in FPGA devices, that provides transport for Ethernet traffic running at 100 Gbit/s into a long-haul optical network, and regeneration of that OTN signal along the path. In addition to the OTN structure overview, we show how the data are synchronized in the ingress interface, the rate justification and mapping mechanisms, the architecture of the FEC codec, and the FPGAs resource usage. The newest FPGAs allow flexibility and optimal performance for high-speed and high-density designs, as presented in this work. An FPGA platform was used to demonstrate the developed applications in the lab.