Rapid interconnect development using an area accelerated electron beam inspection methodology

Author

Shaw, J. ; Guldi, R. ; Kim, T. ; Corum, D. ; Ritchison, J. ; Oestreich, S. ; Lin, J. ; Weiner, K. ; Davis, K. ; Fiordalice, R.

Author_Institution

SiTD, Texas Instrum. Inc., Dallas, TX, USA

fYear

2002

fDate

2002

Firstpage

33

Lastpage

35

Abstract

This paper describes how a new defect inspection technology and methodology was employed to accelerate the process development and integration learning cycles of a 130 nm advanced logic device. The advanced yield management technique to be described is designed specifically for back-end-of-line (BEOL) module development. Through case studies, the application of this technology for process and integration development is demonstrated. Specifically, we discuss how the application of this technology accelerates the development cycle by allowing for a greater number of cycles of learning. The devices used in this study employed a low k dielectric (k < 3.0), a SiC etch-stop scheme, and several levels of Cu interconnect.

Keywords

copper; electron beam applications; inspection; integrated circuit interconnections; integrated circuit yield; integrated logic circuits; 130 nm; BEOL module development; Cu; Cu interconnect; SiC; SiC etch-stop scheme; advanced logic device; advanced yield management technique; area accelerated electron beam inspection; back-end-of-line module development; defect inspection methodology; low k dielectric; rapid interconnect development; Acceleration; Chip scale packaging; Dielectric devices; Electron beams; Filtering; Inspection; Logic devices; Testing; Throughput; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014878

Filename

1014878