Computational complexity analysis of set-bin-packing problem

Given a set of items and a set of bins of the same capacity, the Set-Bin-Packing Problem (SEP) is to pack all the items into the bins where each item is associated with a set and a bin can contain items as long as the number of distinct elements in the union of the sets does not exceed the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In FPGA terminology, an item, an element in an item, a bin, capacity correspond to a gate, an input signal of a gate, an LUT, and the number of input terminals of an LUT. In this paper, the computational complexity of SEP is studied with respect to three parameters; the number of input terminals of an LUT, the upper bound of the number of input signals of a gate, and the upper bound of the number of fanout gates of a signal, respectively. Our result reveals that SEP remains NP-hard for small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters