Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview)

The continuous shrinking of CMOS transistors in the nano-scale era poses many manufacturing and reliability challenges such as process variation, sub-threshold leakage, power dissipation, increased circuit noise sensitivity, and reliability concerns due to transient (e.g. radiation-induced soft errors) and permanent (e.g. transistor aging) failures [1, 2]. State-of-the-art FPGAs, pushed by the ever-increasing demands on higher performance and lower power, use the latest advancements in CMOS technology [3, 4], and thus they share most of these challenges. Therefore, to guarantee the required lifetime of FPGA-mapped systems in the field, proper techniques at various levels should be devised. Transistor aging, as an important factor, causes an increase in the magnitude of threshold voltage, which in turn slows down the switching speed of the transistor and leads to timing failures and faster wear-out rates [5]. To properly deal with this issue in FPGAs, it requires modeling, monitoring and mitigation at device and architecture levels as well as the tool-chain at user level.