Density Enhancement Study for a Bipolar VLSI Masterslice Chip using 4 Layers of Metal Part 1: Masterslice Chip Design - General Aspects

The System/370 chip which was developed in IBM East Fishkill, USA [1] is designed on a logic masterslice or gate-array chip with almost 5000 automatically wired circuits. Based on the good experience with this chip and based on the Boeblingen contributions to this design, we decided to continue the development effort to determine the optimum way for increased logic circuit density, improved chip productivity and better power-performance on masterslices within the present technology environment. The easiest way to improve logic density on a masterslice chip is to reduce the channel pitch by shrinking groundrules. This way, however, is always limited to certain boundaries of a given technology and might require high capital investment for improved equipment. Another approach is to spend an additional level of wiring [6]. In a placement and wiring study, which is described in Part 2 of this paper, it was proven with actual logic from the IBM 4331 System that an additional wiring layer will reduce the active chip area by more than a factor of two. The average net length with its corresponding capacitance is also reduced which increases the performance. Encouraged by this significant density improvement, a masterslice chip with almost 10 000 circuits was designed using 2.55.¿m groundrules, 3 layers of metal for wiring and one for power and I/O redistribution.