DocumentCode
1901521
Title
An automatic test pattern generation program for large ASICs
Author
Liu, Dick L. ; Galivanche, Rajesh ; Hsu, C.C.
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
fYear
1989
fDate
2-4 Oct 1989
Firstpage
244
Lastpage
248
Abstract
An automatic test pattern generation program (ATPG) is described for large, application-specific integrated circuits (ASICs) designed with a scan path technique. This program was implemented with an improved deterministic test generation algorithm that makes use of a split model for circuit representation and multiple testability heuristics for efficient search. The program can also interface to a hardware accelerator to speed up the test compaction process
Keywords
application specific integrated circuits; automatic testing; circuit CAD; automatic test pattern generation program; circuit representation; deterministic test generation algorithm; hardware accelerator; large ASICs; multiple testability heuristics; scan path technique; split model; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design automation; Hardware; Large scale integration; Model driven engineering; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-1971-6
Type
conf
DOI
10.1109/ICCD.1989.63364
Filename
63364
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