• DocumentCode
    1901541
  • Title

    Precise exception handling for a self-timed processor

  • Author

    Richardson, William E. ; Brunvand, Erik

  • Author_Institution
    Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
  • fYear
    1995
  • fDate
    2-4 Oct 1995
  • Firstpage
    32
  • Lastpage
    37
  • Abstract
    Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended. However, providing a precise exception model for a self-timed micropipelined processor can be difficult, since the processor state does not change at uniformly discrete intervals. We present a precise exception method implemented for Fred, a self-timed, decoupled, pipelined computer architecture with out-of-order instruction completion
  • Keywords
    exception handling; parallel architectures; self-adjusting systems; Fred; decoupled computer architectures; instruction level parallelism; micropipelined processor; multiple concurrent processes; out-of-order instruction completion; pipelined computer architecture; precise exception handling; self-timed processor; self-timed queues; self-timed systems; Circuits; Cities and towns; Clocks; Computer architecture; Computer science; Microprocessors; Out of order; Parallel processing; Pipelines; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-7165-3
  • Type

    conf

  • DOI
    10.1109/ICCD.1995.528787
  • Filename
    528787