DocumentCode
1901689
Title
Ultralow-power CMOS/SOI LSI design for future mobile systems
Author
Douseki, T. ; Yamada, J. ; Kyuragi, H.
Author_Institution
Telecommun. Energy Labs., NTT Corp., Kanagawa, Japan
fYear
2002
fDate
13-15 June 2002
Firstpage
6
Lastpage
9
Abstract
Ultralow-power CMOS/SOI circuit technology that uses fully-depleted SOI and multi-threshold (MT) CMOS circuits makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to 1 /spl sim/ 10 mW without any speed loss. We overview the ultralow-power CMOS/SOI circuit technology and some ultralow-voltage LSIs based on MTCMOS/SOI circuits.
Keywords
CMOS integrated circuits; VLSI; integrated circuit design; large scale integration; low-power electronics; mixed analogue-digital integrated circuits; mobile communication; silicon-on-insulator; 0.5 V; 1 to 10 mW; Si; fully-depleted SOI; mobile systems; multi-threshold CMOS circuits; supply voltage reduction; ultralow-power CMOS/SOI LSI design; ultralow-voltage LSIs; CMOS technology; Circuits; Energy dissipation; Large scale integration; Leakage current; MOSFETs; Mobile communication; Power dissipation; Radio frequency; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015028
Filename
1015028
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